1. Field of the Invention
The present invention relates to the fabrication of a protection diode array.
2. Discussion of the Related Art
In many practical configurations, it is necessary to fabricate protection diode arrays such as the one illustrated in FIG. 1A in which diodes D1-1, D1-2, D1-3, . . . D1-n have first terminals T1-1, T1-2, T1-3, . . . T1-n, that are respectively connected to lines to be protected, and a second common terminal T2 connected to a reference voltage such as ground or another line. In the illustrated example and in the following description, all the diodes have a common cathode, but it is apparent that a symmetric array, in which the anodes are common and the cathodes are individually connected to lines to be protected, can be similarly fabricated.
The most conventional way to fabricate, in the form of a monolithic component, a diode array such as the one of FIG. 1A is illustrated in the cross-sectional view of FIG. 1B. The array is realized in the form of a monolithic semiconductor component in an N-type substrate 1. P-type regions P1-1, P1-2, P1-3, . . . P1-n are formed at the surface of substrate 1. A highly doped N-type region, N1, is formed on the lower surface of substrate 1. The upper surface of the component is coated with an insulation layer, conventionally a silicon oxide layer 2; metallizations M1-1, M1-2, M1-3, . . . M1-n contact each region P1-1 to P1-n. A metallization M2 is formed over the rear surface and contacts region N1. Each metallization M1-1 to M1-n constitutes the anode of one of diodes D1 to Dn; the rear surface metallization M2 constitutes the common cathode of all these diodes. Conventionally, the component is mounted, for example by welding, on a metallic base 3.
Conventionally, as schematically represented by the top view of FIG. 1C, the metallic base 3 on which component 1 is mounted, is part of a lead frame. The lead frame is a metallic plate that is suitably cut off to include base 3, strips T1-1 to T1-n+2 forming pins (indicated by hatched areas in FIG. 1C) and linking elements (indicated by circles in FIG. 1C) that are merely intended to mechanically maintain the frame during the connection phase. The connection phase includes connecting by means of a wire W, usually a gold thread, each metallization region M1-1 to M1-n of the chip at one end of a strip forming the pin T1 to T1-n. The last two pins T1-n+1 and T1-n+2 are extensions of base 3. Indeed, the machines for welding a thread between two points (a pin and a metallization) are very sophisticated and precise, and it is very difficult to adjust these machines to make them perform determined welding operations between points having a determined difference in level (such as a pin and the upper surface of a chip) and points having a dissimilar difference in level or a same level (such as a pin and the base).
Once a chip is welded to the base of a lead frame and its metallization regions are connected by gold threads to elements forming the pins of the frame, the chip is embedded in plastic, for example according to the pattern indicated by the dashed line 5 of FIG. 1C; then the linking elements between the pins of the lead frame (regions indicated by circles in FIG. 1C) are cut away and removed. FIG. 1C is a schematic and is only useful for illustrating the problem that the invention aims at solving. In practice, the casing used can be a casing including two rows of pins, such as a casing S020.
For reasons that clearly appear referring to the top view of FIG. 1C, the cathode contact that corresponds to base 3 is practically unavoidably connected to outermost pins, for example pin T1-n+2 and the facing pin. These cathode terminals (a single terminal could be sufficient, but two are generally provided) are often connected to ground and, for practical reasons, the user may desire that these ground terminals be disposed close to specific pins, for example, the third pin on one side and the seventh pin on the other side, and not close to the outermost pins (pins 10 and 20 or 1 and 11 in the case of a casing including ten pins on each side). Such a mounting is very difficult with the structure of FIG. 1C.
Additionally, the technique for manufacturing semiconductor components has evolved over time. Whereas the various implantation and diffusions steps in a semiconductor chip are theoretically the most complex operations and the ones that impart its function to the component, the combination of these steps (usually referred to in the technique as "front end" operations) are now frequently less expensive than the steps required for the mounting of the chip in a casing (commonly referred to in the technique as "back end" operations). It is now frequently more advantageous to increase the complexity of the diffusion pattern in the silicon in order to simplify mounting, thus reducing the overall cost of the component.